totem pole output transistor transistor logic

Transistors Q 1 and Q 2 are both arranged in the same manner that we’ve seen for transistor Q 1 in all the other TTL circuits. If you have a minute to shed some light on this that would be muchly appreciated.Let’s examine the following TTL circuit and analyze its operation: If that transistor is on, current is sunk from 2k, across that 800ohm dropping enough voltage to turn the bottom one on? This then turns the transistor connected to the diode off because there isn't enough voltage left to fwd bias the diode, turning the top half of the totem on, i.e the output goes high? Not sure that's correct. When the inputs are both high, this causes enough leakage current to flow that the transistor following the input is turn on, where does the voltage come from here to fwd bias this transistor? is Vce negative here with respect to the collector of the first transistor? This is where it gets confusing for me. this turns that transistor on, draining current through that 1.6k resistor down to ground, the voltage drop across the 1k resistor turns that output transistor on, sinking current to ground causing a low output. The diode is forward biased by the voltage across the 2k resistor, is it the diode drop that is turning the transistor on? i'm not really clear on the role of that diode there.

the transistor connected to the emitter of this one is therefore also off. In it's quiescent state (i.e both inputs at 0) the transistor following the input transistor is off due to no leakage current through the emitter > collector from the input transistor. Hi pal, I have no-one else to ask so if you don't mind correcting me if i'm wrong in how i think this works? Here's a potato quality pic of the NOR circuit from my textbook. Hopefully someone can illuminate this for me, i'd really appreciate it :) I've looked online but the only stuff i can find are either open collector OR/AND gates or totem pole NOR/NAND gates.

The textbook then went on to explain that adding a common emitter transistor before the totem pole would invert this signal causing the NOR/NAND to go OR/AND, but i just can't visualiuse how that would work. Hi guys, was just doing some reading in a textbook for a project i'm planning, was reading about TTL architecture specifically was just reading about NOR/NAND gates and how they use totem pole outputs for low output impedance.įrom what i understand how this works is the 'top' part of the totem holds the output high until a high input through the logic sinks current from the output to ground through the bottom transistor, causing a logic low.

Totem pole output transistor transistor logic